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Logic Design and Verification Using SystemVerilog (Revised)

De (autor): Donald Thomas

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Logic Design and Verification Using SystemVerilog (Revised) - Donald Thomas

Logic Design and Verification Using SystemVerilog (Revised)

De (autor): Donald Thomas

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Donald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.
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Donald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.
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